Power amplifier circuit

ABSTRACT

A power amplifier circuit, comprising: a final stage, comprising first and second amplifying elements for amplifying an input signal; and a driver stage, for providing the input signal to the final stage. The circuit is characterized by a first capacitor coupled between an input of the first amplifying element and an output of the second amplifying element; and a second capacitor coupled between an input of the second amplifying element and an output of the first amplifying element.

TECHNICAL FIELD

The present invention relates to power amplifiers, and particularly to power amplifiers for use in the generation of radio-frequency signals.

BACKGROUND OF THE INVENTION

Power amplifier nonlinearities have a significant impact on the overall performance of modern digital communication systems.

The AM-PM (amplitude modulation to phase modulation) non-ideal transfer characteristic plays a predominant role amongst power amplifier non-idealities. A great deal of effort is invested in complex baseband/digital pre-distortion schemes to sense and counteract its effects. For such schemes to be efficient and viable, however, the spread of AM-PM should be minimized in the analogue domain in the first place. Furthermore, this should ideally be achieved across the whole frequency range of operation, especially for power amplifiers that are required to operate over a very wide frequency range.

A further non-linearity is variation of the power amplifier gain with temperature. In order to ease the requirements placed on the rest of the transmit-chain blocks, such variation should be kept as small as possible.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provided a power amplifier circuit, comprising: a final stage, comprising first and second amplifying elements for amplifying an input signal; and a driver stage, for providing the input signal to the final stage. The circuit is characterized by a first capacitor coupled between an input of the first amplifying element and an output of the second amplifying element; and a second capacitor coupled between an input of the second amplifying element and an output of the first amplifying element.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example, to the following drawings, in which:

FIG. 1 shows a power amplifier circuit according to an embodiment of the present invention;

FIG. 2 shows a circuit for generating the bias currents utilized in the power amplifier circuits according to embodiments of the present invention;

FIG. 3 shows a circuit for adapting the resistor R_(B) in FIG. 2;

FIG. 4 shows a circuit for adapting the device ratio M₁:M₂ in FIG. 2;

FIG. 5 shows the dependence of input capacitance at the amplifying elements with amplitude of signal swing;

FIG. 6 shows the AM-PM transfer characteristic for the power amplifier circuit in FIG. 1 at a temperature of 60° C.; and

FIG. 7 shows the AM-PM transfer characteristic for the power amplifier circuit in FIG. 1 at a temperature of 120° C.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a power amplifier circuit 10 according to an embodiment of the present invention.

The power amplifier circuit 10 comprises a final stage, for amplifying an input voltage and outputting via a load, and a driver stage (illustrated in part) used to interface the final stage to a mixer circuit (not illustrated).

Two inputs 12, 14 provide an input signal from the mixer circuit to the driver stage. The inputs 12, 14 are coupled to an inductor 16, such that an electrical signal corresponding to the input signal is induced in the inductor 16. A first end of the inductor 16 is coupled to an input gate of a first amplifying element M₁₁, and a second end of the inductor 16 is coupled to the input gate of a second amplifying element M₁₂. A variable capacitor 18 is coupled between the two ends of the inductor 16 and between the input gates of the two amplifying elements M₁₁ and M₁₂.

In order to set the DC level at the input gates of the amplifying elements M₁₁ and M₁₂, a current source 20 provides a biasing current I_(BIAS), coupled between a supply voltage V_(DD) and the drain terminal of a transistor 22. The drain terminal of the transistor 22 is also connected to the gate terminal of the transistor 22, and the source terminal is coupled to ground. A node between the current source 20 and the drain terminal of the transistor 22 is coupled to the inductor 16 part of the way along its length. In one embodiment the node is coupled to the mid-point of the inductor 16. In this way the current I_(BIAS) supplied by the current source 20 sets the DC level at the input of each amplifying element M₁₁ and M₁₂. The operation of the current source 20 will be described in greater detail below.

The final stage of the amplifier circuit 10 comprises main amplifying elements M₁₁ and M₁₂, which in the illustrated embodiment are transistors. The gate terminal of each transistor is coupled to a respective end of the inductor 16, as described above, for receiving the signal to be amplified. The source terminal of each transistor is coupled to a reference voltage (in the illustrated example, ground), and the drain terminal of each transistor is coupled, indirectly, to a supply voltage V_(DD). An inductor L₁₁ is coupled in series between the drain terminal of the transistor M₁₁ and the supply voltage V_(DD); that is, a first end of the inductor L₁₁ is coupled to the drain terminal of the transistor M₁₁ while a second end of the inductor L₁₁ is coupled to the supply voltage V_(DD). A further inductor L₁₂ is coupled in series between the drain terminal of the transistor M₁₂ and the supply voltage V_(DD); that is, a first end of the inductor L₁₂ is coupled to the drain terminal of the transistor M₁₂ while a second end of the inductor L₁₂ is coupled to the supply voltage V_(DD). Further, the respective second ends of the inductors L₁₁ and L₁₂ are coupled to each other. A capacitor C₁ is coupled between the respective first ends of the inductors L₁₁ and L₁₂.

Inductors L₁₁ and L₁₂ form part of a transformer, and are magnetically coupled (by a coupling factor k) to an inductor L₂. The inductor L₂ is coupled in parallel with a second capacitor C₂ and a load R_(L). In one embodiment, the load R_(L) is an antenna. A reference voltage (in the illustrated embodiment, ground) is coupled to a terminal each of the inductor L₂, the capacitor C₂ and the load R_(L).

According to embodiments of the present invention, the DC voltage at the drains of the amplifying transistors M₁₁ and M₁₂ is further controlled by coupling cascode devices M₂₁ and M₂₂ between the drain terminals of the devices and the inductors L₁₁ and L₁₂. That is, a first cascode device M₂₁ (in the illustrated embodiment, a transistor) is configured with its source terminal connected to the drain terminal of the amplifying element M₁₁, and its drain terminal connected to the first end of the inductor L₁₁ (and also a first terminal of the capacitor C₁); a second cascode device M₂₂ (in the illustrated embodiment, a transistor) is configured with its source terminal connected to the drain terminal of the amplifying element M₁₂, and its drain terminal connected to the first end of the inductor L₁₂ (and also a second terminal of the capacitor C₁). The gate terminals of both cascode devices M₂₁ and M₂₂ are controlled by a biasing circuit comprising a current source 24 generating current I_(CTAT) coupled between a supply voltage VDD and a first terminal of a resistor 26. The second terminal of the resistor 26 is coupled to a reference voltage (in the illustrated embodiment, ground). The gate terminals of the cascode devices M₂₁ and M₂₂ are connected to a node between the current source 24 and the resistor 26.

In operation of the power amplifier circuit 10, an oscillating signal is input via the inputs 12, 14 and a corresponding signal induced in the inductor 16, which is biased by the current I_(BIAS) developed in current source 20. Signals to be amplified are thus input to the amplifying elements M₁₁ and M₁₂, and corresponding amplified signals generated in the inductors L₁₁ and L₁₂. A further signal is induced in the inductor L₂, and eventually output to the load R_(L).

As set out above, it is desirable to minimize the spread of the AM-PM transfer characteristic of any power amplifier circuit. There are two main contributors to such a spread. The first is the signal-swing dependent impedance looking into the gate terminals of the amplifying elements M₁₁ and M₁₂. FIG. 5 shows the reduction observed in the input capacitance of the final stage with increasing signal swing. At relatively low signal swing, the capacitance is relatively high, while at relatively high signal swing the capacitance is relatively low. This results in an upward shift of the driver stage resonant frequency as signal-swing increases and thus also an increase in phase-lead in the phase transfer of the driver.

The second major contributor to AM-PM spread is the dependence of the drain current (i.e. output) of the final stage devices (M₁₁ and M₁₂) on their drain-to-source voltage. Phase shifts in that voltage due to the frequency selective nature of the transformer (i.e. inductors L₁₁, L₁₂ and L₂) also have an effect. This is because the final stage devices have a finite output impedance, and also because they enter the triode (or Ohmic) region of operation while the output signal is momentarily low during its cycle. Mixing effects between the fundamental signal V_(in) cos(ω_(o)t) applied at the gate terminals and phase-shifted higher harmonics V_(o1) cos(ω_(o)t), V_(o2) cos(2ω_(o)t+φ), . . . appearing at the drain terminals result in phase lag in the transfer function of the fundamental through the output stage as the signal swing increases, where ω_(o) corresponds to the fundamental frequency of operation. To explicitly show this, assume the generic equation for the device drain-source current:

I _(DS) ˜KV _(in) cos ω_(o) t·[1+λV _(o1) cos ω_(o) t+λV _(o2) cos(2ω_(o) t+φ)+ . . . ]  (1)

where the first term models linear gain by virtue of parameter K, while the second term models the dependence of the current on the output (drain) voltage (by virtue of parameter λ). Expanding equation (1) and keeping terms only at the fundamental frequency gives

$\begin{matrix} {{{{\left. I_{DS} \right.\sim{{KV}_{in}\left\lbrack {1 + {\frac{1}{2}\lambda \; V_{o\; 2}\cos \; \phi}} \right\rbrack}} \cdot \cos}\; \omega_{o}t} - {{{{KV}_{in}\left\lbrack {\frac{1}{2}\lambda \; V_{o\; 2}\sin \; \phi} \right\rbrack} \cdot \sin}\; \omega_{o}t} + \ldots} & (2) \end{matrix}$

The first term in equation (2) represents the in-phase term (in-phase with the driving voltage) whereas the second term represents the quadrature-phase term. We therefore can write

I _(DS) ˜KV _(in) cos(ω_(o) t+θ)  (3)

where the phase-lag θ is given by

$\begin{matrix} {\theta = {\tan^{- 1}\frac{\frac{1}{2}\lambda \; V_{o\; 2}\sin \; \phi}{1 + {\frac{1}{2}\lambda \; V_{o\; 2}\cos \; \phi}}}} & (4) \end{matrix}$

Since the phase shift φ at the second harmonic of the output signal is −90°<φ<0, the term sin φ in the denominator of Equation (4) is negative. Thus θ is also negative as it should be, since it represents a phase-lag. In the limiting case λ=0 (i.e. where the device current does not depend on the output voltage) the phase lag goes to zero.

According to embodiments of the present invention the variation of the input capacitance of the final stage is reduced by introducing cross-coupling capacitors 50, 52. These capacitors cause weak local positive feedback and thus reduce variation of the input capacitance. In particular, a first capacitor 50 is connected between the gate terminal of the second amplifying element M₁₂ and the drain terminal of the first amplifying element M₁₁. A second capacitor 52 is connected between the gate terminal of the first amplifying element M₁₁ and the drain terminal of the second amplifying element M₁₂. The capacitors 50, 52 also help to compensate for any detrimental effects caused by the gate-drain parasitic capacitances of M₁₁ and M₁₂ such as the Miller effect.

In further embodiments of the present invention, the phase lead in the driver transfer can be used to compensate for the phase lag inherent in the final stage. For this we introduce a capacitor digital-to-analogue converter (CDAC) 18 at the output of the driver stage. That is, the variable capacitor 18, coupled between the respective gate terminals of the amplifying elements M₁₁ and M₁₂, can be set to a capacitance value which closely matches the phase lag of the final stage to the phase lead in the driver transfer. This allows operation over a wide frequency range as required, but also gives fine control in placing the driver resonance slightly below the required frequency of operation. As the signal-swing increases, the driver resonance moves slightly up in frequency thus introducing a small amount of phase-lead in its transfer characteristic. In this way, the phase lead in the driver coarsely compensates for the phase lag inherent in the final stage.

In one embodiment, therefore, the capacitance of the variable capacitor 18 is varied according to the required frequency of operation, so as to place the driver resonance slightly below the required frequency of operation.

The overall AM-PM characteristic of the power amplifier circuit 10 is shown in FIG. 6, at a temperature of 60° C. The transfer characteristic of the driver stage is illustrated by the line marked 600; the transfer characteristic of the final stage is illustrated by the line marked 602; and the transfer characteristic of the overall device (i.e. the combination of driver and final stages) is illustrated by the line marked 604. As can be seen, the phase lead of the driver stage at relatively high input signal-swing partially compensates for the phase lag of the final stage at relatively high input signal-swing. The transfer characteristic for their combination is thus smoother over the input range.

As described above, a common problem associated with power amplifier circuits is variation of the power amplifier gain with temperature. Ideally such variation should be kept as small as possible. According to embodiments of the present invention, variation of the amplifier gain with temperature is reduced by biasing the input terminals of the amplifying elements with a current which is proportional to absolute temperature, and by controlling the output terminals of the amplifying elements with cascode devices which are themselves biased with a current which is complementary to absolute temperature. In embodiments of the present invention, the current used to bias the input terminals of the amplifying elements is proportional to absolute temperature (i.e. directly proportional, I∝T) with a constant which is positive; the current used to bias the gate terminals of the cascode devices is proportional to absolute temperature (i.e. directly proportional, I∝T) with a constant which is negative. The two constants do not generally have the same magnitude.

In one embodiment the current source 20 generates a current I_(BIAS) which is proportional to absolute temperature, with a constant of proportionality equal to (1+β) where β is a positive real number. The current source 24 generates a current γI_(CTAT) which is complementary to absolute temperature where γ is a scaling constant.

Those skilled in the art will appreciate that the current sources 20, 24 may form different parts of the same circuit. That is, the same circuit may be used to generate both I_(BIAS) and I_(CTAT). FIG. 2 shows a circuit 100 according to embodiments of the present invention which may be used to generate both currents.

The circuit 100 first generates a current which is proportional to absolute temperature I_(PTAT), and then generates the further currents I_(CTAT) and I_(BIAS) by manipulating I_(PTAT) in combination with various reference currents. A bias resistor R_(B) is coupled between a reference voltage (in the illustrated embodiment, ground) and the source terminal of a transistor M₂. The drain terminal of the device M₂ is coupled to a supply voltage V_(DD) (via a current mirror CM₁). A further transistor M₁ is configured with its drain terminal also coupled to the supply voltage V_(DD) via the current mirror CM₁, and its source terminal coupled to a reference voltage (in the illustrated embodiment, ground). The gate and drain terminals of the device M₁ are connected together, and the gate terminals of the devices M₁ and M₂ are also connected together. The devices M₁ and M₂ thus form a current mirror.

The difference in gate-source voltages (ΔV_(GS)) of the two devices M₁ and M₂ varies proportionally to absolute temperature, and thus a current I_(PTAT) is generated flowing into the drain terminal of the transistor M₂ which also varies proportionally to absolute temperature according to the following relationship:

$\begin{matrix} {I_{PTAT} = {\frac{2}{R_{B}^{2}\mu \; C_{ox}\frac{W}{L}}\left( {1 - \frac{1}{\sqrt{N}}} \right)^{2}}} & (5) \end{matrix}$

where μ, C_(ox) and

$\frac{W}{L}$

are the mobility, oxide capacitance and aspect ratio of the devices respectively. N is the M₁/M₂ device ratio, i.e. 1:N=M₁:M₂. The mobility μ varies inversely with absolute temperature, and thus I_(PTAT) varies proportionally to absolute temperature.

The value of I_(PTAT) can be controlled by varying R_(B) and/or N. Schemes for varying these quantities are illustrated in FIGS. 3 and 4, respectively.

FIG. 3 shows part of a circuit 200 for varying the biasing resistor R_(B), and comprises a first resistor 202, having resistance R. One or more further resistors 204 are connected in series with the first resistor 202 (in FIG. 3, four further resistors 204 a-d) are illustrated) and a short-circuit path provided around each further resistor 204. Switches 206 are provided in each short-circuit path and may be used selectively to couple the further resistors 204 into the conductive path, so selectively increasing the resistance of the combination of all resistors 202, 204. The total resistance of all resistors in the conductive path provides R_(B). The resistors 202, 204 may individually have the same or different resistances. An advantage of providing different resistances is that more variation in the value of R_(B) is allowed due to the greater number of different combination possible. Those skilled in the art will appreciate that alternative schemes may be provided to change the value of R_(B). For example, the resistors 202, 204 may be connected in parallel rather than series without substantially affecting the operation of the circuit.

FIG. 4 shows a circuit 300 for varying the value of N, the device ratio between M₁ and M₂. The circuit 300 shows transistor M₁, with its drain terminal coupled to a first intermediate node 302, its gate terminal connected to its drain terminal, and its source terminal connected to a reference voltage (in the illustrated embodiment, ground). The second transistor, M₂, actually comprises a plurality of transistor elements 304 coupled in parallel with each other. That is, the gate terminals of each transistor element 304 are connected to the gate terminal of the transistor M₁, the drain terminals are all connected to a second intermediate node 306, and the source terminals are all connected to the reference voltage (i.e. ground). In the illustrated embodiment there are five transistor elements 304 but any number may be provided. Switches 308 are provided in the conduction path for each transistor element 304 but one, and by selectively switching the transistor elements 304 into and out of the conduction path from the second intermediate node 306 to the reference voltage, the effective aspect ratio of the device M₂ can be varied (and hence IV).

I_(PTAT) may thus be varied as required by varying N and/or R_(B).

Returning to FIG. 2, a further transistor M₃ is configured with its gate terminal coupled to the gate terminals of M₁ and M₂, its source terminal coupled to a reference voltage (in the illustrated embodiment, ground), and its drain terminal coupled to a supply voltage V_(DD). The device ratio M₂:M₃ is equal to 1:1 and thus the current into the drain terminal of the device M₃ is equal to I_(PTAT). A current source 27 is coupled between the supply voltage and the drain terminal of the device M₃, and provides a constant reference current. In one embodiment, the reference current is generated by way of a bandgap voltage V_(BG) over a resistance R. A node coupled between the drain terminal of the device M₃ and the current source 27 can thus draw off a current equal to

${\frac{V_{BG}}{R} - I_{PTAT}} = {I_{CTAT}.}$

I_(CTAT) and I_(PTAT) can then be combined to create the currents used to bias the amplifying elements M₁₁ and M₁₂ and the cascode devices M₂₁ and M₂₂. The circuit 100 comprises two current mirrors CM₁ and CM₂. The first current mirror CM₁ has four connections, two to the drain terminals of the devices M₁ and M₂, one to the supply voltage V_(DD), and a further connection to a first output node 28 of the circuit 100. The current flowing towards the first output node 28 from the current mirror CM₁ can be made to mirror I_(PTAT), flowing into the drain terminal of device M₂. By manipulation of the device ratios in the current mirror CM₁, the current flowing towards the output node 28 from CM₁ can be made proportional to I_(PTAT), scaled by a factor β. In one embodiment, β can be made variable, as will be shown below.

The second current mirror CM₂ also has four connections, and is coupled between the node referred to above, drawing off I_(CTAT), a reference voltage (in the illustrated embodiment, ground), the first output node 28, and a second output node 30. Again, by manipulation of the device ratios in the current mirror CM2, the current flowing towards the first output node 28 can be made equal to I_(CTAT), and the current flowing towards the second output node 30 equal to γI_(CTAT), where γ is a scaling constant.

The first output node 28 provides I_(BIAS) and is thus equivalent to the current source 20 shown in FIG. 1. The second output node 30 provides γI_(CTAT) and is equivalent to the current source 24 shown in FIG. 1. The scaling constant γ allows further close control of the biasing current, as well as control over the choice of resistance value for the resistor 26 (cf FIG. 1).

The biasing current generated at the first output node 28 is thus equal to:

$\begin{matrix} \begin{matrix} {I_{BIAS} = {{\beta \; I_{PTAT}} - I_{CTAT}}} \\ {= {{\beta \; I_{PTAT}} - \left( {\frac{V_{BG}}{R} - I_{PTAT}} \right)}} \\ {= {{\left( {\beta + 1} \right)I_{PTAT}} - \frac{V_{BG}}{R}}} \end{matrix} & (6) \end{matrix}$

From equation (6) it is clear that I_(BIAS) varies proportionally with absolute temperature (as I_(PTAT) varies proportionally with absolute temperature) and that variation can be controlled by varying the value of β. As will be clear from the description above, the value of β is determined by the device ratio in the current mirror CM₁. Those skilled in the art will appreciate that this may be varied by using a scheme as illustrated in FIG. 4, whereby the value of N is varied by selectively switching transistor elements into or out of a conduction path in the current mirror CM₁. Likewise, the value of γ may be varied by selectively switching transistor elements into or out of a conduction path in the current mirror CM₂.

The power amplifier circuit 10 thus comprises an amplifier whose input (DC level) is biased using a current which varies in a way which is proportional to absolute temperature. The output (DC level) of the amplifier is controlled indirectly via one or more cascode devices whose gate terminals are biased with a current which varies in a way which is complementary to absolute temperature. The inventors have found that the best performance is achieved when the temperature variation of the current biasing the input is generally greater (i.e. steeper slope) than the temperature variation of the current which biases the gates of the cascode device(s). In this way, the gain variation with temperature can be reduced from more than 2 dB to less than 1 dB over a typical working temperature range (e.g. −40° C. to 120° C.) without any penalty in the large-signal behaviour of the circuit (i.e. AM-AM and compression point).

FIG. 7 shows the overall AM-PM characteristic of the power amplifier circuit 10 at a temperature of 120° C. The transfer characteristic of the driver stage is illustrated by the line marked 700; the transfer characteristic of the final stage is illustrated by the line marked 702; and the transfer characteristic of the overall device (i.e. the combination of driver and final stages) is illustrated by the line marked 704. By comparison with the device at 60° C. (see FIG. 6), it can be seen that relatively little change has taken place with the change in temperature.

The present invention thus provides a power amplifier circuit in which the phase lag of the final stage is compensated for (at least partially) by the phase lead in the driver stage. By providing capacitors cross-coupled between the inputs and outputs of the amplifying elements, the variation in the final stage capacitance can be reduced. In further embodiments, a capacitor digital-to-analogue converter coupled between the outputs of the driver stage enable the resonant frequency of the driver stage to be controlled, so as to match the phase lead of the driver stage to the phase lag of the final stage for any given frequency of operation.

Those skilled in the art will appreciate that various amendments and alterations can be made to the embodiments described above without departing from the scope of the invention as defined in the claims appended hereto. 

What is claimed is:
 1. A power amplifier circuit, comprising: a final stage, comprising first and second amplifying elements for amplifying an input signal; and a driver stage, for providing the input signal to the final stage, characterized by a first capacitor coupled between an input of the first amplifying element and an output of the second amplifying element; and a second capacitor coupled between an input of the second amplifying element and an output of the first amplifying element.
 2. The power amplifier circuit according to claim 1, wherein the first and second capacitors act to reduce variation in the input capacitance of the final stage.
 3. The power amplifier circuit according to claim 1 or 2, wherein the final stage is configured to apply a first phase-shift transfer characteristic to the input signal, and wherein the driver stage is configured to apply a second phase-shift transfer characteristic to the input signal, such that the first and second phase-shift transfer characteristics combine to at least partially cancel each other over a range of input signal values.
 4. The power amplifier circuit according to claim 3, wherein the first phase-shift transfer characteristic applies a zero phase shift at relatively low input signal values, and a positive phase shift at relatively high input signal values, and wherein the second phase-shift transfer characteristic applies a zero phase shift at relatively low input signal values, and a negative phase shift at relatively high input signal values.
 5. The power amplifier circuit according to claim 3 or 4, wherein the driver stage comprises a capacitive digital-to-analogue converter.
 6. The power amplifier circuit according to claim 5, wherein the capacitive digital-to-analogue converter comprises a variable capacitor, the capacitance being variable to adjust the second phase-shift transfer characteristic.
 7. The power amplifier circuit according to any one of the preceding claims, wherein the first amplifying element comprises a first transistor, and the second amplifying element comprises a second transistor.
 8. The power amplifier circuit according to claim 7, wherein the driver stage is coupled to the gate terminals of said first and second transistors.
 9. The power amplifier circuit according to claim 7 or 8, wherein the first capacitor is connected between the drain terminal of the second transistor and the gate terminal of the first transistor, and wherein the second capacitor is connected between the drain terminal of the first transistor and the gate terminal of the second transistor.
 10. The power amplifier circuit according to any one of the preceding claims, further comprising a transformer for coupling the first and second amplifying elements to a load.
 11. A transmitter, comprising a power amplifier circuit according to any one of the preceding claims, and an antenna coupled to the power amplifier circuit. 